Teledyne-lecroy QPHY-SATA Manuel d'utilisateur télécharger pdf (Page 33)

QPHY-SATA Software Option

915745 Rev G 33

Figure 13. Amplitude Imbalance measurement on an MFTP pattern

The following tests measure the jitter, Total (Tj) and Deterministic (Dj), of the transmitter.

TSG-09 – Gen1 (1.5Gb/s) TJ at Connector, Clock to Data fBAUD/500

TSG-10 – Gen1 (1.5Gb/s) DJ at Connector, Clock to Data fBAUD/500

TSG-11 – Gen2 (3.0Gb/s) TJ at Connector, Clock to Data fBAUD/500

TSG-12 – Gen2 (3.0 GB/s) DJ at Connector, Clock to Data fBAUD/500

In the past, these tests had different implementations for products running at 1.5Gb/s and 3.0Gb/s. Currently, the

implementation is the same, but the test names have been left as is. The jitter is measured using a phase-locked

loop (PLL) to recover the clock. To tune the clock recovery to the precise response dictated by the Jitter Transfer

Function in the SATA specification, follow the calibration procedure for jitter measurement devices. Jitter is

measured on HFTP, MFTP and SSOP. The SSOP pattern is optional.

1 2 ... 28 29 30 31 32 33 34 35 36 37 38 ... 44 45

Pas de commentaire

Teledyne-lecroy QPHY-SATA Manuel d'utilisateur Page 33