Teledyne-lecroy QPHY-ENET Manuel d'utilisateur télécharger pdf (Page 61)

QPHY-ENET Software Option

QPHY-ENET Operator’s Manual Rev G

Step 2: Master TX_TCLK Jitter

This step measures both unfiltered and filtered TX_TCLK jitter in Master mode.

Note: This measurement requires access to the master TX_TCLK signal. This clock can be probed on one of the pins of the PHY chip using

an active probe. Contact your PHY chip vendor for information on the location of this signal.

1. Attach an active or differential probe (Minimum Bandwidth 1.5GHz) to the TX_TCLK signal to the DUT.

On the oscilloscope’s Ethernet Tests menu, enter the channel to which this probe is connected as “Master

TX_TCLK”.

2. Apply power to the Device Under Test and configure it for normal operation in the Master mode. A clock

signal should appear on the channel to which the probe is attached.

3. Configure the Link Partner for normal operation in the Slave mode.

4. Connect the DUT to the Link Partner using a short UTP patch cable to verify a valid link exists between

the two devices.

5. Select 1000Base-T in the Select Standard field.

6. Select Master TX_TCLK Jitter in the Select Test field.

7. Click the Set Up and Start Test control to begin the test. Acquire between 100ms and 1s worth of data

(in multiple acquisitions).

8. Parameter P1 is the peak-peak jitter on the TX_TCLK relative to an un-jittered reference. The reference

for this measurement is computed on each acquisition. Parameter P2 is a constant; it is the “worst Jtxout”

for the master, from the Jtxout values tab, that was present when “Setup and Start Test” was pressed. P3

is the filtered peak-peak jitter the track of P1 and P4 is the sum of P2 and P3.

The result in P1 passes if it is less than 1.4ns. The result in P4 passes if it is less than 0.3ns.

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Teledyne-lecroy QPHY-ENET Manuel d'utilisateur Page 61